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Searched refs:XCVR_PLL_DIG_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h27166 #define XCVR_PLL_DIG_BASE (0x41030224u) macro
27168 #define XCVR_PLL_DIG ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
27170 #define XCVR_PLL_DIG_BASE_ADDRS { XCVR_PLL_DIG_BASE }
DRV32M1_zero_riscy.h26297 #define XCVR_PLL_DIG_BASE (0x41030224u) macro
26299 #define XCVR_PLL_DIG ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
26301 #define XCVR_PLL_DIG_BASE_ADDRS { XCVR_PLL_DIG_BASE }