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Searched refs:XCVR_PHY_PHY_FSK_MISC_MSK_EN (Results 1 – 11 of 11) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/cfgs_rv32m1/
Dfsl_xcvr_ant_config.c79 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
105 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_ble_config.c70 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c67 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c67 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c68 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_msk_config.c68 XCVR_PHY_PHY_FSK_MISC_MSK_EN(1) |
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c68 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c68 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c68 XCVR_PHY_PHY_FSK_MISC_MSK_EN(0) |
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26554 #define XCVR_PHY_PHY_FSK_MISC_MSK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_M… macro
DRV32M1_zero_riscy.h25710 #define XCVR_PHY_PHY_FSK_MISC_MSK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_M… macro