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Searched refs:XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK (Results 1 – 11 of 11) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/cfgs_rv32m1/
Dfsl_xcvr_ant_config.c61 XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
89 XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_ble_config.c55 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(0) |
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c52 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c52 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c54 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_msk_config.c53 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c53 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c53 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c53 .phy_fsk_cfg = XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(1) |
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26477 #define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_C… macro
DRV32M1_zero_riscy.h25633 #define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_C… macro