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Searched refs:XCVR_PHY_FSK_STAT_CFO_EST_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26593 #define XCVR_PHY_FSK_STAT_CFO_EST_MASK (0xFF0000U) macro
26595 …(((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_CFO_EST_SHIFT)) & XCVR_PHY_FSK_STAT_CFO_EST_MASK)
DRV32M1_zero_riscy.h25749 #define XCVR_PHY_FSK_STAT_CFO_EST_MASK (0xFF0000U) macro
25751 …(((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_CFO_EST_SHIFT)) & XCVR_PHY_FSK_STAT_CFO_EST_MASK)