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Searched refs:XCVR_PHY_FSK_STAT_AA_MATCHED_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26584 #define XCVR_PHY_FSK_STAT_AA_MATCHED_MASK (0x2U) macro
26586 …t32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_AA_MATCHED_SHIFT)) & XCVR_PHY_FSK_STAT_AA_MATCHED_MASK)
DRV32M1_zero_riscy.h25740 #define XCVR_PHY_FSK_STAT_AA_MATCHED_MASK (0x2U) macro
25742 …t32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_AA_MATCHED_SHIFT)) & XCVR_PHY_FSK_STAT_AA_MATCHED_MASK)