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Searched refs:XCVR_PHY_BASE (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c707 …*(uint32_t *)(XCVR_PHY_BASE+0xC) = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_… in XCVR_Configure()
709 …*(uint32_t *)(XCVR_PHY_BASE+0xC) = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_… in XCVR_Configure()
711 *(uint32_t *)(XCVR_PHY_BASE+0x18) = mode_config->phy_fad_ctrl; in XCVR_Configure()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26628 #define XCVR_PHY_BASE (0x41030400u) macro
26630 #define XCVR_PHY ((XCVR_PHY_Type *)XCVR_PHY_BASE)
26632 #define XCVR_PHY_BASE_ADDRS { XCVR_PHY_BASE }
DRV32M1_zero_riscy.h25784 #define XCVR_PHY_BASE (0x41030400u) macro
25786 #define XCVR_PHY ((XCVR_PHY_Type *)XCVR_PHY_BASE)
25788 #define XCVR_PHY_BASE_ADDRS { XCVR_PHY_BASE }