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Searched refs:XCVR_MISC (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Ddbg_ram_capture.c46 …XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK /* Make PKT RAM availa… in dbg_ram_init()
60 XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* force to idle */ in dbg_ram_release()
61 …XCVR_MISC->PACKET_RAM_CTRL &= ~(XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK /* Make PKT RAM avai… in dbg_ram_release()
116 temp = XCVR_MISC->PACKET_RAM_CTRL; in unpack_sequential_data()
119 XCVR_MISC->PACKET_RAM_CTRL = temp; in unpack_sequential_data()
164 …xcvr_ctrl_pkt_ram_0_sel = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MA… in unpack_simul_data()
165 …xcvr_ctrl_pkt_ram_1_sel = XCVR_MISC->PACKET_RAM_CTRL | XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MAS… in unpack_simul_data()
170 XCVR_MISC->PACKET_RAM_CTRL = xcvr_ctrl_pkt_ram_0_sel; in unpack_simul_data()
175 XCVR_MISC->PACKET_RAM_CTRL = xcvr_ctrl_pkt_ram_1_sel; in unpack_simul_data()
179 …XCVR_MISC->PACKET_RAM_CTRL = xcvr_ctrl_pkt_ram_0_sel; /* leave selection set to bank 0 of packet R… in unpack_simul_data()
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Dfsl_xcvr.c669 temp = XCVR_MISC->XCVR_CTRL; in XCVR_Configure()
679 XCVR_MISC->XCVR_CTRL = temp; in XCVR_Configure()
682 XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK; in XCVR_Configure()
1039 …XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TS… in XCVR_Configure()
1380 …while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_… in XCVR_Configure()
1614 temp = XCVR_MISC->XCVR_CTRL; in XCVR_SetIRQMapping()
1617 XCVR_MISC->XCVR_CTRL = temp; in XCVR_SetIRQMapping()
1628 …return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_… in XCVR_GetIRQMapping()
1632 …return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_… in XCVR_GetIRQMapping()
1720 …temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SH… in XCVR_OverrideChannel()
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Dfsl_xcvr_trim.c385 …while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_… in rx_dc_sample_average()
457 …while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_… in rx_dc_sample_average_long()
515 …while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_… in rx_dc_est_average()
788 temp = XCVR_MISC->XCVR_CTRL; in DCOC_DAC_INIT_Cal()
792 XCVR_MISC->XCVR_CTRL = temp; in DCOC_DAC_INIT_Cal()
985 XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack; in DCOC_DAC_INIT_Cal()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26385 #define XCVR_MISC ((XCVR_CTRL_Type *)XCVR_MISC_BASE) macro
26389 #define XCVR_CTRL_BASE_PTRS { XCVR_MISC }
DRV32M1_zero_riscy.h25541 #define XCVR_MISC ((XCVR_CTRL_Type *)XCVR_MISC_BASE) macro
25545 #define XCVR_CTRL_BASE_PTRS { XCVR_MISC }