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Searched refs:XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h25922 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK (0x80U) macro
25928 …2_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK)
DRV32M1_zero_riscy.h25078 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK (0x80U) macro
25084 …2_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK)