1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_WDOG32_H_
9 #define _FSL_WDOG32_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup wdog32
15 * @{
16 */
17
18
19 /*******************************************************************************
20 * Definitions
21 *******************************************************************************/
22 /*! @name Unlock sequence */
23 /*@{*/
24 #define WDOG_FIRST_WORD_OF_UNLOCK (WDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */
25 #define WDOG_SECOND_WORD_OF_UNLOCK ((WDOG_UPDATE_KEY >> 16U)& 0xFFFFU) /*!< Second word of unlock sequence */
26 /*@}*/
27
28 /*! @name Refresh sequence */
29 /*@{*/
30 #define WDOG_FIRST_WORD_OF_REFRESH (WDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */
31 #define WDOG_SECOND_WORD_OF_REFRESH ((WDOG_REFRESH_KEY >> 16U)& 0xFFFFU) /*!< Second word of refresh sequence */
32 /*@}*/
33 /*! @name Driver version */
34 /*@{*/
35 /*! @brief WDOG32 driver version 2.0.0. */
36 #define FSL_WDOG32_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
37 /*@}*/
38
39 /*! @brief Describes WDOG32 clock source. */
40 typedef enum _wdog32_clock_source
41 {
42 kWDOG32_ClockSource0 = 0U, /*!< Clock source 0 */
43 kWDOG32_ClockSource1 = 1U, /*!< Clock source 1 */
44 kWDOG32_ClockSource2 = 2U, /*!< Clock source 2 */
45 kWDOG32_ClockSource3 = 3U, /*!< Clock source 3 */
46 } wdog32_clock_source_t;
47
48 /*! @brief Describes the selection of the clock prescaler. */
49 typedef enum _wdog32_clock_prescaler
50 {
51 kWDOG32_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */
52 kWDOG32_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */
53 } wdog32_clock_prescaler_t;
54
55 /*! @brief Defines WDOG32 work mode. */
56 typedef struct _wdog32_work_mode
57 {
58 bool enableWait; /*!< Enables or disables WDOG32 in wait mode */
59 bool enableStop; /*!< Enables or disables WDOG32 in stop mode */
60 bool enableDebug; /*!< Enables or disables WDOG32 in debug mode */
61 } wdog32_work_mode_t;
62
63 /*! @brief Describes WDOG32 test mode. */
64 typedef enum _wdog32_test_mode
65 {
66 kWDOG32_TestModeDisabled = 0U, /*!< Test Mode disabled */
67 kWDOG32_UserModeEnabled = 1U, /*!< User Mode enabled */
68 kWDOG32_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */
69 kWDOG32_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */
70 } wdog32_test_mode_t;
71
72 /*! @brief Describes WDOG32 configuration structure. */
73 typedef struct _wdog32_config
74 {
75 bool enableWdog32; /*!< Enables or disables WDOG32 */
76 wdog32_clock_source_t clockSource; /*!< Clock source select */
77 wdog32_clock_prescaler_t prescaler; /*!< Clock prescaler value */
78 wdog32_work_mode_t workMode; /*!< Configures WDOG32 work mode in debug stop and wait mode */
79 wdog32_test_mode_t testMode; /*!< Configures WDOG32 test mode */
80 bool enableUpdate; /*!< Update write-once register enable */
81 bool enableInterrupt; /*!< Enables or disables WDOG32 interrupt */
82 bool enableWindowMode; /*!< Enables or disables WDOG32 window mode */
83 uint16_t windowValue; /*!< Window value */
84 uint16_t timeoutValue; /*!< Timeout value */
85 } wdog32_config_t;
86
87 /*!
88 * @brief WDOG32 interrupt configuration structure.
89 *
90 * This structure contains the settings for all of the WDOG32 interrupt configurations.
91 */
92 enum _wdog32_interrupt_enable_t
93 {
94 kWDOG32_InterruptEnable = WDOG_CS_INT_MASK, /*!< Interrupt is generated before forcing a reset */
95 };
96
97 /*!
98 * @brief WDOG32 status flags.
99 *
100 * This structure contains the WDOG32 status flags for use in the WDOG32 functions.
101 */
102 enum _wdog32_status_flags_t
103 {
104 kWDOG32_RunningFlag = WDOG_CS_EN_MASK, /*!< Running flag, set when WDOG32 is enabled */
105 kWDOG32_InterruptFlag = WDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */
106 };
107
108 /*******************************************************************************
109 * API
110 *******************************************************************************/
111
112 #if defined(__cplusplus)
113 extern "C" {
114 #endif /* __cplusplus */
115
116 /*!
117 * @name WDOG32 Initialization and De-initialization
118 * @{
119 */
120
121 /*!
122 * @brief Initializes the WDOG32 configuration structure.
123 *
124 * This function initializes the WDOG32 configuration structure to default values. The default
125 * values are:
126 * @code
127 * wdog32Config->enableWdog32 = true;
128 * wdog32Config->clockSource = kWDOG32_ClockSource1;
129 * wdog32Config->prescaler = kWDOG32_ClockPrescalerDivide1;
130 * wdog32Config->workMode.enableWait = true;
131 * wdog32Config->workMode.enableStop = false;
132 * wdog32Config->workMode.enableDebug = false;
133 * wdog32Config->testMode = kWDOG32_TestModeDisabled;
134 * wdog32Config->enableUpdate = true;
135 * wdog32Config->enableInterrupt = false;
136 * wdog32Config->enableWindowMode = false;
137 * wdog32Config->windowValue = 0U;
138 * wdog32Config->timeoutValue = 0xFFFFU;
139 * @endcode
140 *
141 * @param config Pointer to the WDOG32 configuration structure.
142 * @see wdog32_config_t
143 */
144 void WDOG32_GetDefaultConfig(wdog32_config_t *config);
145
146 /*!
147 * @brief Initializes the WDOG32 module.
148 *
149 * This function initializes the WDOG32.
150 * To reconfigure the WDOG32 without forcing a reset first, enableUpdate must be set to true
151 * in the configuration.
152 *
153 * Example:
154 * @code
155 * wdog32_config_t config;
156 * WDOG32_GetDefaultConfig(&config);
157 * config.timeoutValue = 0x7ffU;
158 * config.enableUpdate = true;
159 * WDOG32_Init(wdog_base,&config);
160 * @endcode
161 *
162 * @param base WDOG32 peripheral base address.
163 * @param config The configuration of the WDOG32.
164 */
165 void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config);
166
167 /*!
168 * @brief De-initializes the WDOG32 module.
169 *
170 * This function shuts down the WDOG32.
171 * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled.
172 *
173 * @param base WDOG32 peripheral base address.
174 */
175 void WDOG32_Deinit(WDOG_Type *base);
176
177 /* @} */
178
179 /*!
180 * @name WDOG32 functional Operation
181 * @{
182 */
183
184 /*!
185 * @brief Enables the WDOG32 module.
186 *
187 * This function writes a value into the WDOG_CS register to enable the WDOG32.
188 * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and
189 * this register has not been written in this WCT while the function is called.
190 *
191 * @param base WDOG32 peripheral base address.
192 */
WDOG32_Enable(WDOG_Type * base)193 static inline void WDOG32_Enable(WDOG_Type *base)
194 {
195 base->CS |= WDOG_CS_EN_MASK;
196 }
197
198 /*!
199 * @brief Disables the WDOG32 module.
200 *
201 * This function writes a value into the WDOG_CS register to disable the WDOG32.
202 * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and
203 * this register has not been written in this WCT while the function is called.
204 *
205 * @param base WDOG32 peripheral base address
206 */
WDOG32_Disable(WDOG_Type * base)207 static inline void WDOG32_Disable(WDOG_Type *base)
208 {
209 base->CS &= ~WDOG_CS_EN_MASK;
210 }
211
212 /*!
213 * @brief Enables the WDOG32 interrupt.
214 *
215 * This function writes a value into the WDOG_CS register to enable the WDOG32 interrupt.
216 * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and
217 * this register has not been written in this WCT while the function is called.
218 *
219 * @param base WDOG32 peripheral base address.
220 * @param mask The interrupts to enable.
221 * The parameter can be a combination of the following source if defined:
222 * @arg kWDOG32_InterruptEnable
223 */
WDOG32_EnableInterrupts(WDOG_Type * base,uint32_t mask)224 static inline void WDOG32_EnableInterrupts(WDOG_Type *base, uint32_t mask)
225 {
226 base->CS |= mask;
227 }
228
229 /*!
230 * @brief Disables the WDOG32 interrupt.
231 *
232 * This function writes a value into the WDOG_CS register to disable the WDOG32 interrupt.
233 * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and
234 * this register has not been written in this WCT while the function is called.
235 *
236 * @param base WDOG32 peripheral base address.
237 * @param mask The interrupts to disabled.
238 * The parameter can be a combination of the following source if defined:
239 * @arg kWDOG32_InterruptEnable
240 */
WDOG32_DisableInterrupts(WDOG_Type * base,uint32_t mask)241 static inline void WDOG32_DisableInterrupts(WDOG_Type *base, uint32_t mask)
242 {
243 base->CS &= ~mask;
244 }
245
246 /*!
247 * @brief Gets the WDOG32 all status flags.
248 *
249 * This function gets all status flags.
250 *
251 * Example to get the running flag:
252 * @code
253 * uint32_t status;
254 * status = WDOG32_GetStatusFlags(wdog_base) & kWDOG32_RunningFlag;
255 * @endcode
256 * @param base WDOG32 peripheral base address
257 * @return State of the status flag: asserted (true) or not-asserted (false). @see _wdog32_status_flags_t
258 * - true: related status flag has been set.
259 * - false: related status flag is not set.
260 */
WDOG32_GetStatusFlags(WDOG_Type * base)261 static inline uint32_t WDOG32_GetStatusFlags(WDOG_Type *base)
262 {
263 return (base->CS & (WDOG_CS_EN_MASK | WDOG_CS_FLG_MASK));
264 }
265
266 /*!
267 * @brief Clears the WDOG32 flag.
268 *
269 * This function clears the WDOG32 status flag.
270 *
271 * Example to clear an interrupt flag:
272 * @code
273 * WDOG32_ClearStatusFlags(wdog_base,kWDOG32_InterruptFlag);
274 * @endcode
275 * @param base WDOG32 peripheral base address.
276 * @param mask The status flags to clear.
277 * The parameter can be any combination of the following values:
278 * @arg kWDOG32_InterruptFlag
279 */
280 void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask);
281
282 /*!
283 * @brief Sets the WDOG32 timeout value.
284 *
285 * This function writes a timeout value into the WDOG_TOVAL register.
286 * The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and
287 * this register has not been written in this WCT while the function is called.
288 *
289 * @param base WDOG32 peripheral base address
290 * @param timeoutCount WDOG32 timeout value, count of WDOG32 clock ticks.
291 */
WDOG32_SetTimeoutValue(WDOG_Type * base,uint16_t timeoutCount)292 static inline void WDOG32_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)
293 {
294 base->TOVAL = timeoutCount;
295 }
296
297 /*!
298 * @brief Sets the WDOG32 window value.
299 *
300 * This function writes a window value into the WDOG_WIN register.
301 * The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and
302 * this register has not been written in this WCT while the function is called.
303 *
304 * @param base WDOG32 peripheral base address.
305 * @param windowValue WDOG32 window value.
306 */
WDOG32_SetWindowValue(WDOG_Type * base,uint16_t windowValue)307 static inline void WDOG32_SetWindowValue(WDOG_Type *base, uint16_t windowValue)
308 {
309 base->WIN = windowValue;
310 }
311
312 /*!
313 * @brief Unlocks the WDOG32 register written.
314 *
315 * This function unlocks the WDOG32 register written.
316 *
317 * Before starting the unlock sequence and following the configuration, disable the global interrupts.
318 * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire.
319 * After the configuration finishes, re-enable the global interrupts.
320 *
321 * @param base WDOG32 peripheral base address
322 */
WDOG32_Unlock(WDOG_Type * base)323 static inline void WDOG32_Unlock(WDOG_Type *base)
324 {
325 if ((base->CS) & WDOG_CS_CMD32EN_MASK)
326 {
327 base->CNT = WDOG_UPDATE_KEY;
328 }
329 else
330 {
331 base->CNT = WDOG_FIRST_WORD_OF_UNLOCK;
332 base->CNT = WDOG_SECOND_WORD_OF_UNLOCK;
333 }
334 }
335
336 /*!
337 * @brief Refreshes the WDOG32 timer.
338 *
339 * This function feeds the WDOG32.
340 * This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted.
341 *
342 * @param base WDOG32 peripheral base address
343 */
WDOG32_Refresh(WDOG_Type * base)344 static inline void WDOG32_Refresh(WDOG_Type *base)
345 {
346 if ((base->CS) & WDOG_CS_CMD32EN_MASK)
347 {
348 base->CNT = WDOG_REFRESH_KEY;
349 }
350 else
351 {
352 base->CNT = WDOG_FIRST_WORD_OF_REFRESH;
353 base->CNT = WDOG_SECOND_WORD_OF_REFRESH;
354 }
355 }
356
357 /*!
358 * @brief Gets the WDOG32 counter value.
359 *
360 * This function gets the WDOG32 counter value.
361 *
362 * @param base WDOG32 peripheral base address.
363 * @return Current WDOG32 counter value.
364 */
WDOG32_GetCounterValue(WDOG_Type * base)365 static inline uint16_t WDOG32_GetCounterValue(WDOG_Type *base)
366 {
367 return base->CNT;
368 }
369
370 /*@}*/
371
372 #if defined(__cplusplus)
373 }
374 #endif /* __cplusplus */
375
376 /*! @}*/
377
378 #endif /* _FSL_WDOG32_H_ */
379
