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Searched refs:TRNG_SCR5C_R5_1_CT_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h20206 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) macro
20208 … (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
DRV32M1_zero_riscy.h21034 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) macro
21036 … (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)