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Searched refs:TIR (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_rtc.c367 base->TIR |= tmp32; in RTC_EnableInterrupts()
430 base->TIR &= (uint32_t)(~tmp32); in RTC_DisableInterrupts()
464 if (RTC_TIR_TMIE_MASK == (RTC_TIR_TMIE_MASK & base->TIR)) in RTC_GetEnabledInterrupts()
468 if (RTC_TIR_FSIE_MASK == (RTC_TIR_FSIE_MASK & base->TIR)) in RTC_GetEnabledInterrupts()
473 if (RTC_TIR_TPIE_MASK == (RTC_TIR_TPIE_MASK & base->TIR)) in RTC_GetEnabledInterrupts()
479 if (RTC_TIR_SIE_MASK == (RTC_TIR_SIE_MASK & base->TIR)) in RTC_GetEnabledInterrupts()
485 if (RTC_TIR_LCIE_MASK == (RTC_TIR_LCIE_MASK & base->TIR)) in RTC_GetEnabledInterrupts()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15426 …__IO uint32_t TIR; /**< RTC Tamper Interrupt Register, offset: 0x3C … member
DRV32M1_zero_riscy.h16254 …__IO uint32_t TIR; /**< RTC Tamper Interrupt Register, offset: 0x3C … member