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Searched refs:TIMING21 (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c1116 XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; in XCVR_Configure()
1150 XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ in XCVR_Configure()
1257 XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init+GFSK_250K_RX_WD_ONLY_ADJUST; in XCVR_Configure()
1326 XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; in XCVR_Configure()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h29205 __IO uint32_t TIMING21; /**< TSM_TIMING21, offset: 0x84 */ member
DRV32M1_zero_riscy.h28336 __IO uint32_t TIMING21; /**< TSM_TIMING21, offset: 0x84 */ member