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Searched refs:TCR (Results 1 – 7 of 7) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpspi.c206 base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | in LPSPI_MasterInit()
268 base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | in LPSPI_SlaveInit()
449 …srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIF… in LPSPI_MasterSetDelayTimes()
612 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_MasterTransferBlocking()
660 base->TCR = in LPSPI_MasterTransferBlocking()
661 …(base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_M… in LPSPI_MasterTransferBlocking()
722 base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); in LPSPI_MasterTransferBlocking()
761 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_MasterTransferNonBlocking()
837 base->TCR = in LPSPI_MasterTransferNonBlocking()
838 …(base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_M… in LPSPI_MasterTransferNonBlocking()
[all …]
Dfsl_lpspi_edma.c166 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_MasterTransferEDMA()
245 …base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSP… in LPSPI_MasterTransferEDMA()
412 handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); in LPSPI_MasterTransferEDMA()
417 transferConfigTx.destAddr = (uint32_t) & (base->TCR); in LPSPI_MasterTransferEDMA()
618 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_SlaveTransferEDMA()
696 base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | in LPSPI_SlaveTransferEDMA()
Dfsl_lpspi.h791 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1); in LPSPI_SetFrameSize()
Dfsl_dac.h369 base->TCR = LPDAC_TCR_SWTRG_MASK; in DAC_DoSoftwareTriggerFIFO()
Dfsl_rtc.c216 base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); in RTC_Init()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h9930 …__O uint32_t TCR; /**< DAC Trigger Control Register, offset: 0x28 */ member
11550 __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ member
15414 …__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC … member
DRV32M1_zero_riscy.h10074 …__O uint32_t TCR; /**< DAC Trigger Control Register, offset: 0x28 */ member
11694 __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ member
16242 …__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC … member