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Searched refs:STAT (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpuart.c402 base->STAT |= temp; in LPUART_Init()
431 while (0 == (base->STAT & LPUART_STAT_TC_MASK)) in LPUART_Deinit()
447 base->STAT |= temp; in LPUART_Deinit()
614 temp = base->STAT; in LPUART_GetStatusFlags()
633 temp = (uint32_t)base->STAT; in LPUART_ClearStatusFlags()
646 base->STAT = temp; in LPUART_ClearStatusFlags()
672 while (!(base->STAT & LPUART_STAT_TDRE_MASK)) in LPUART_WriteBlocking()
696 while (!(base->STAT & LPUART_STAT_RDRF_MASK)) in LPUART_ReadBlocking()
1033 if (LPUART_STAT_OR_MASK & base->STAT) in LPUART_TransferHandleIRQ()
1036 base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); in LPUART_TransferHandleIRQ()
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Dfsl_lpadc.h389 return base->STAT; in LPADC_GetStatusFlags()
402 base->STAT = mask; in LPADC_ClearStatusFlags()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h653 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ member
12298 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ member
20645 __I uint8_t STAT; /**< Status register, offset: 0x90 */ member
DRV32M1_zero_riscy.h624 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ member
12442 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ member
21473 __I uint8_t STAT; /**< Status register, offset: 0x90 */ member