Searched refs:SR (Results 1 – 9 of 9) sorted by relevance
61 while (!(base->SR & (kMU_Tx0EmptyFlag >> regIndex))) in MU_SendMsg()73 while (!(base->SR & (kMU_Rx0FullFlag >> regIndex))) in MU_ReceiveMsg()83 while (base->SR & MU_SR_FUP_MASK) in MU_SetFlags()112 base->SR = MU_SR_RDIP_MASK; in MU_BootCoreB()131 while (!(base->SR & MU_SR_RDIP_MASK)) in MU_BootCoreB()161 base->SR = sr; in MU_HardwareResetOtherCore()173 while (!(base->SR & MU_SR_RAIP_MASK)) in MU_HardwareResetOtherCore()183 while (!(base->SR & MU_SR_RDIP_MASK)) in MU_HardwareResetOtherCore()203 base->SR = sr; in MU_HardwareResetOtherCore()215 while (!(base->SR & MU_SR_RAIP_MASK)) in MU_HardwareResetOtherCore()[all …]
286 return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT; in MU_GetFlags()321 …return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_… in MU_GetStatusFlags()380 base->SR = (mask & regMask); in MU_ClearStatusFlags()458 base->SR = MU_SR_NMIC_MASK; in MU_ClearNmi()544 while (base->SR & MU_SR_RS_MASK) in MU_ResetBothSides()663 return (mu_power_mode_t)((base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT); in MU_GetOtherCorePowerMode()
500 if (RTC_SR_TIF_MASK == (RTC_SR_TIF_MASK & base->SR)) in RTC_GetStatusFlags()504 if (RTC_SR_TOF_MASK == (RTC_SR_TOF_MASK & base->SR)) in RTC_GetStatusFlags()508 if (RTC_SR_TAF_MASK == (RTC_SR_TAF_MASK & base->SR)) in RTC_GetStatusFlags()513 if (RTC_SR_MOF_MASK == (RTC_SR_MOF_MASK & base->SR)) in RTC_GetStatusFlags()519 if (RTC_SR_TIDF_MASK == (RTC_SR_TIDF_MASK & base->SR)) in RTC_GetStatusFlags()637 if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) in RTC_IncrementMonotonicCounter()
178 base->SR &= ~RTC_SR_TCE_MASK; in RTC_Deinit()361 base->SR |= RTC_SR_TCE_MASK; in RTC_StartTimer()373 base->SR &= ~RTC_SR_TCE_MASK; in RTC_StopTimer()
516 return (base->SR); in LPSPI_GetStatusFlags()574 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ in LPSPI_ClearStatusFlags()
816 tkcs = base->SR & CAU3_SR_TKCS_MASK; in cau3_process_task_completion()819 tkcs = base->SR & CAU3_SR_TKCS_MASK; in cau3_process_task_completion()834 tkcs = base->SR & CAU3_SR_TKCS_MASK; in cau3_process_task_completion()882 while ((base->SR & CAU3_SR_TKCS_MASK) == CAU3_SR_TKCS_INITRUN) in cau3_initialize_inst_memory()887 if ((base->SR & CAU3_SR_TKCS_MASK) != CAU3_SR_TKCS_STOPNOERR) in cau3_initialize_inst_memory()889 return (0xbad00000U + (base->SR & CAU3_SR_TKCS_MASK)); /* exit with error */ in cau3_initialize_inst_memory()892 base->SR = CAU3_SR_TCIRQ_MASK; /* clear the TCIRQ interrupt flag */ in cau3_initialize_inst_memory()
550 tkcs = base->SR & CAU3_SR_TKCS_MASK; in cau3_process_task_completion()553 tkcs = base->SR & CAU3_SR_TKCS_MASK; in cau3_process_task_completion()568 tkcs = base->SR & CAU3_SR_TKCS_MASK; in cau3_process_task_completion()616 while ((base->SR & CAU3_SR_TKCS_MASK) == CAU3_SR_TKCS_INITRUN) in cau3_initialize_inst_memory()621 if ((base->SR & CAU3_SR_TKCS_MASK) != CAU3_SR_TKCS_STOPNOERR) in cau3_initialize_inst_memory()623 return (0xbad00000U + (base->SR & CAU3_SR_TKCS_MASK)); /* exit with error */ in cau3_initialize_inst_memory()626 base->SR = CAU3_SR_TCIRQ_MASK; /* clear the TCIRQ interrupt flag */ in cau3_initialize_inst_memory()
1509 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ member11537 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ member14046 __IO uint32_t SR; /**< Status Register, offset: 0x60 */ member15416 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ member
1292 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ member11681 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ member14728 __IO uint32_t SR; /**< Status Register, offset: 0x60 */ member16244 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ member
