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Searched refs:SPM_DCDCSC_DCDC_VBAT_DIV_CTRL (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_spm.h704 …DCSC = (base->DCDCSC & ~SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) | SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(divide… in SPM_SetDcdcVbatAdcMeasure()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19103 #define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_VB… macro
DRV32M1_zero_riscy.h19931 #define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_VB… macro