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Searched refs:SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_spm.c173 base->DCDCC4 = SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK | SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK | in SPM_SetDcdcIntegratorConfig()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19180 #define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK (0x80000U) macro
19186 …t32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK)
DRV32M1_zero_riscy.h20008 #define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK (0x80000U) macro
20014 …t32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK)