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Searched refs:SPM_DCDCC3_DCDC_VBAT_VALUE_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_spm.c150 …base->DCDCC3 = (base->DCDCC3 & ~SPM_DCDCC3_DCDC_VBAT_VALUE_MASK) | SPM_DCDCC3_DCDC_VBAT_VALUE(valu… in SPM_BypassDcdcBattMonitor()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19149 #define SPM_DCDCC3_DCDC_VBAT_VALUE_MASK (0x1CU) macro
19151 …(uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT)) & SPM_DCDCC3_DCDC_VBAT_VALUE_MASK)
DRV32M1_zero_riscy.h19977 #define SPM_DCDCC3_DCDC_VBAT_VALUE_MASK (0x1CU) macro
19979 …(uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT)) & SPM_DCDCC3_DCDC_VBAT_VALUE_MASK)