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Searched refs:SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19155 #define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
19157 …int32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK)
DRV32M1_zero_riscy.h19983 #define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
19985 …int32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK)