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Searched refs:SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_spm.c124 …CDCC2 &= ~(SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK | SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK); in SPM_SetDcdcBattMonitor()
129 base->DCDCC2 |= SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK; in SPM_SetDcdcBattMonitor()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19136 #define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U) macro
19138 …(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK)
DRV32M1_zero_riscy.h19964 #define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U) macro
19966 …(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK)