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Searched refs:SOSCDIV (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c30 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
31 #define SCG_SOSCDIV_SOSCDIV2_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV…
32 #define SCG_SOSCDIV_SOSCDIV3_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV3_MASK) >> SCG_SOSCDIV_SOSCDIV…
337 SCG->SOSCDIV = in CLOCK_InitSysOsc()
Dfsl_clock.h1134 uint32_t reg = SCG->SOSCDIV; in CLOCK_SetSysOscAsyncClkDiv()
1149 SCG->SOSCDIV = reg; in CLOCK_SetSysOscAsyncClkDiv()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16188 __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ member
DRV32M1_zero_riscy.h17016 __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ member