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Searched refs:SOSCCSR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c346 SCG->SOSCCSR = tmp8; in CLOCK_InitSysOsc()
349 while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) in CLOCK_InitSysOsc()
354 SCG->SOSCCSR |= (uint32_t)config->monitorMode; in CLOCK_InitSysOsc()
361 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc()
375 SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_DeinitSysOsc()
382 if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */ in CLOCK_GetSysOscFreq()
Dfsl_clock.h1174 return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCERR_MASK); in CLOCK_IsSysOscErr()
1182 SCG->SOSCCSR |= SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_ClearSysOscErr()
1195 uint32_t reg = SCG->SOSCCSR; in CLOCK_SetSysOscMonitorMode()
1201 SCG->SOSCCSR = reg; in CLOCK_SetSysOscMonitorMode()
1211 return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK); in CLOCK_IsSysOscValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16187 …__IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: … member
DRV32M1_zero_riscy.h17015 …__IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: … member