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Searched refs:SMC_SSRS_SCG_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h18387 #define SMC_SSRS_SCG_MASK (0x1000U) macro
18393 … (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK)
DRV32M1_zero_riscy.h19215 #define SMC_SSRS_SCG_MASK (0x1000U) macro
19221 … (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK)