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Searched refs:SMC_SRS_SCG_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_msmc.h132 kSMC_SourceScg = SMC_SRS_SCG_MASK, /*!< SCG loss of lock or loss of clock */
152 … SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h18243 #define SMC_SRS_SCG_MASK (0x1000U) macro
18249 …) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK)
DRV32M1_zero_riscy.h19071 #define SMC_SRS_SCG_MASK (0x1000U) macro
19077 …) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK)