1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_MSMC_H_
9 #define _FSL_MSMC_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup msmc */
14 /*! @{*/
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief MSMC driver version 2.1.0. */
25 #define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
26 /*@}*/
27
28 /*!
29 * @brief Power Modes Protection
30 */
31 typedef enum _smc_power_mode_protection
32 {
33 kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
34 kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */
35 kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */
36 kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */
37 kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK |
38 SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode. */
39 } smc_power_mode_protection_t;
40
41 /*!
42 * @brief Power Modes in PMSTAT
43 */
44 typedef enum _smc_power_state
45 {
46 kSMC_PowerStateRun = 1U, /*!< 0000_0001 - Current power mode is RUN */
47 kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode */
48 kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR */
49 kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
50 } smc_power_state_t;
51
52 /*!
53 * @brief Power Stop Entry Status in PMSTAT
54 */
55 typedef enum _smc_power_stop_entry_status
56 {
57 kSMC_PowerStopEntryAlt0 = 1U, /*!< Indicates a Stop mode entry since this field was last cleared. */
58 kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */
59 kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */
60 kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */
61 kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */
62 kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */
63 } smc_power_stop_entry_status_t;
64
65 /*!
66 * @brief Run mode definition
67 */
68 typedef enum _smc_run_mode
69 {
70 kSMC_RunNormal = 0U, /*!< normal RUN mode. */
71 kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */
72 kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
73 } smc_run_mode_t;
74
75 /*!
76 * @brief Stop mode definition
77 */
78 typedef enum _smc_stop_mode
79 {
80 kSMC_StopNormal = 0U, /*!< Normal STOP mode. */
81 kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */
82 kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */
83 #if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
84 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
85 kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */
86 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
87 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
88 kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */
89 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
90 #else
91 kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */
92 #endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
93 } smc_stop_mode_t;
94
95 /*!
96 * @brief Partial STOP option
97 */
98 typedef enum _smc_partial_stop_mode
99 {
100 kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/
101 kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
102 kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
103 kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/
104 } smc_partial_stop_option_t;
105
106 /*!
107 * @brief SMC configuration status
108 */
109 enum _smc_status
110 {
111 kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/
112 };
113
114 /*!
115 * @brief System Reset Source Name definitions
116 */
117 typedef enum _smc_reset_source
118 {
119 kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */
120 kSMC_SourcePor = SMC_SRS_POR_MASK, /*!< Power on reset */
121 kSMC_SourceLvd = SMC_SRS_LVD_MASK, /*!< Low-voltage detect reset */
122 kSMC_SourceHvd = SMC_SRS_HVD_MASK, /*!< High-voltage detect reset */
123 kSMC_SourceWarm = SMC_SRS_WARM_MASK, /*!< Warm reset. Warm Reset flag will assert if any of the system reset
124 sources in this register assert (SRS[31:8]) */
125 kSMC_SourceFatal = SMC_SRS_FATAL_MASK, /*!< Fatal reset */
126 kSMC_SourceCore =
127 SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */
128 kSMC_SourcePin = SMC_SRS_PIN_MASK, /*!< RESET_B pin reset. */
129 kSMC_SourceMdm = SMC_SRS_MDM_MASK, /*!< MDM reset. */
130 kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK, /*!< Reset Controller timeout reset. */
131 kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */
132 kSMC_SourceScg = SMC_SRS_SCG_MASK, /*!< SCG loss of lock or loss of clock */
133 kSMC_SourceWdog = SMC_SRS_WDOG_MASK, /*!< Watchdog reset */
134 kSMC_SourceSoftware = SMC_SRS_SW_MASK, /*!< Software reset */
135 kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK, /*!< Lockup reset. Core lockup or exception. */
136 kSMC_SourceJtag = SMC_SRS_JTAG_MASK, /*!< JTAG system reset */
137 #if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
138 kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */
139 #endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
140 #if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
141 kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */
142 #endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
143 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
144 kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */
145 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
146 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
147 kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */
148 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
149 /* Source All. */
150 kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK |
151 SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK |
152 SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
153 SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK
154 #if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
155 |
156 SMC_SRS_SECVIO_MASK
157 #endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
158 #if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
159 |
160 SMC_SRS_TAMPER_MASK
161 #endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
162 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
163 |
164 SMC_SRS_CORE0_MASK
165 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
166 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
167 |
168 SMC_SRS_CORE1_MASK
169 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
170 ,
171 } smc_reset_source_t;
172
173 /*!
174 * @brief System reset interrupt enable bit definitions.
175 */
176 typedef enum _smc_interrupt_enable
177 {
178 kSMC_IntNone = 0U, /*!< No interrupt enabled. */
179 kSMC_IntPin = SMC_SRIE_PIN_MASK, /*!< Pin reset interrupt. */
180 kSMC_IntMdm = SMC_SRIE_MDM_MASK, /*!< MDM reset interrupt. */
181 kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt. */
182 kSMC_IntWdog = SMC_SRIE_WDOG_MASK, /*!< Watchdog interrupt. */
183 kSMC_IntSoftware = SMC_SRIE_SW_MASK, /*!< Software reset interrupts. */
184 kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK, /*!< Lock up interrupt. */
185 #if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
186 kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */
187 #endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
188 #if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
189 kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */
190 #endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
191 kSMC_IntAll = SMC_SRIE_PIN_MASK | /*!< All system reset interrupts. */
192 SMC_SRIE_MDM_MASK |
193 SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK | SMC_SRIE_LOCKUP_MASK
194 #if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
195 |
196 SMC_SRIE_CORE0_MASK
197 #endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
198 #if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
199 |
200 SMC_SRIE_CORE1_MASK
201 #endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
202 } smc_interrupt_enable_t;
203
204 /*!
205 * @brief Reset pin filter configuration
206 */
207 typedef struct _smc_reset_pin_filter_config
208 {
209 uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles. */
210 bool enableFilter; /*!< Reset pin filter enable/disable. */
211 #if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
212 bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */
213 #endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
214 } smc_reset_pin_filter_config_t;
215
216 /*******************************************************************************
217 * API
218 ******************************************************************************/
219 #if defined(__cplusplus)
220 extern "C" {
221 #endif /* __cplusplus*/
222
223 /*! @name System mode controller APIs*/
224 /*@{*/
225
226 /*!
227 * @brief Configures all power mode protection settings.
228 *
229 * This function configures the power mode protection settings for
230 * supported power modes in the specified chip family. The available power modes
231 * are defined in the smc_power_mode_protection_t. This should be done at an early
232 * system level initialization stage. See the reference manual for details.
233 * This register can only write once after the power reset.
234 *
235 * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
236 * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls).
237 * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
238 *
239 * @param allowedModes Bitmap of the allowed power modes.
240 */
SMC_SetPowerModeProtection(SMC_Type * base,uint8_t allowedModes)241 static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
242 {
243 base->PMPROT = allowedModes;
244 }
245
246 /*!
247 * @brief Gets the current power mode status.
248 *
249 * This function returns the current power mode stat. Once application
250 * switches the power mode, it should always check the stat to check whether it
251 * runs into the specified mode or not. An application should check
252 * this mode before switching to a different mode. The system requires that
253 * only certain modes can switch to other specific modes. See the
254 * reference manual for details and the smc_power_state_t for information about
255 * the power stat.
256 *
257 * @param base SMC peripheral base address.
258 * @return Current power mode status.
259 */
SMC_GetPowerModeState(SMC_Type * base)260 static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
261 {
262 return (smc_power_state_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT);
263 }
264
265 #if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT)
266 /*!
267 * @brief Gets the result of the previous stop mode entry.
268 *
269 * This function returns the result of the previous stop mode entry.
270 *
271 * @param base SMC peripheral base address.
272 * @return Current power stop entry status.
273 */
SMC_GetStopEntryStatus(SMC_Type * base)274 static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base)
275 {
276 return (smc_power_stop_entry_status_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >> SMC_PMSTAT_STOPSTAT_SHIFT);
277 }
278
279 /*!
280 * @brief Clears all the result of the previous stop mode entry.
281 *
282 * This function clears all the result of the previous stop mode entry.
283 *
284 * @param base SMC peripheral base address.
285 * @return Current power stop entry status.
286 */
SMC_ClearStopEntryStatus(SMC_Type * base)287 static inline void SMC_ClearStopEntryStatus(SMC_Type *base)
288 {
289 /* Only write 0x01 to clear this field, all other writes are ignored. */
290 base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01);
291 }
292
293 #endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */
294
295 /*!
296 * @brief Prepare to enter stop modes
297 *
298 * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
299 */
SMC_PreEnterStopModes(void)300 static inline void SMC_PreEnterStopModes(void)
301 {
302 __disable_irq();
303 __ISB();
304 }
305
306 /*!
307 * @brief Recovering after wake up from stop modes
308 *
309 * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
310 * It is used together with @ref SMC_PreEnterStopModes.
311 */
SMC_PostExitStopModes(void)312 static inline void SMC_PostExitStopModes(void)
313 {
314 __enable_irq();
315 __ISB();
316 }
317
318 /*!
319 * @brief Prepare to enter wait modes
320 *
321 * This function should be called before entering WAIT/VLPW modes..
322 */
SMC_PreEnterWaitModes(void)323 static inline void SMC_PreEnterWaitModes(void)
324 {
325 __disable_irq();
326 __ISB();
327 }
328
329 /*!
330 * @brief Recovering after wake up from stop modes
331 *
332 * This function should be called after wake up from WAIT/VLPW modes.
333 * It is used together with @ref SMC_PreEnterWaitModes.
334 */
SMC_PostExitWaitModes(void)335 static inline void SMC_PostExitWaitModes(void)
336 {
337 __enable_irq();
338 __ISB();
339 }
340
341 /*!
342 * @brief Configure the system to RUN power mode.
343 *
344 * @param base SMC peripheral base address.
345 * @return SMC configuration error code.
346 */
347 status_t SMC_SetPowerModeRun(SMC_Type *base);
348
349 /*!
350 * @brief Configure the system to HSRUN power mode.
351 *
352 * @param base SMC peripheral base address.
353 * @return SMC configuration error code.
354 */
355 status_t SMC_SetPowerModeHsrun(SMC_Type *base);
356
357 /*!
358 * @brief Configure the system to WAIT power mode.
359 *
360 * @param base SMC peripheral base address.
361 * @return SMC configuration error code.
362 */
363 status_t SMC_SetPowerModeWait(SMC_Type *base);
364
365 /*!
366 * @brief Configure the system to Stop power mode.
367 *
368 * @param base SMC peripheral base address.
369 * @param option Partial Stop mode option.
370 * @return SMC configuration error code.
371 */
372 status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
373
374 /*!
375 * @brief Configure the system to VLPR power mode.
376 *
377 * @param base SMC peripheral base address.
378 * @return SMC configuration error code.
379 */
380 status_t SMC_SetPowerModeVlpr(SMC_Type *base);
381
382 /*!
383 * @brief Configure the system to VLPW power mode.
384 *
385 * @param base SMC peripheral base address.
386 * @return SMC configuration error code.
387 */
388 status_t SMC_SetPowerModeVlpw(SMC_Type *base);
389
390 /*!
391 * @brief Configure the system to VLPS power mode.
392 *
393 * @param base SMC peripheral base address.
394 * @return SMC configuration error code.
395 */
396 status_t SMC_SetPowerModeVlps(SMC_Type *base);
397 /*!
398 * @brief Configure the system to LLS power mode.
399 *
400 * @param base SMC peripheral base address.
401 * @return SMC configuration error code.
402 */
403 status_t SMC_SetPowerModeLls(SMC_Type *base);
404
405 #if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
406 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
407 /*!
408 * @brief Configure the system to VLLS0 power mode.
409 *
410 * @param base SMC peripheral base address.
411 * @return SMC configuration error code.
412 */
413 status_t SMC_SetPowerModeVlls0(SMC_Type *base);
414 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
415 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
416 /*!
417 * @brief Configure the system to VLLS2 power mode.
418 *
419 * @param base SMC peripheral base address.
420 * @return SMC configuration error code.
421 */
422 status_t SMC_SetPowerModeVlls2(SMC_Type *base);
423 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
424 #else
425 /*!
426 * @brief Configure the system to VLLS power mode.
427 *
428 * @param base SMC peripheral base address.
429 * @return SMC configuration error code.
430 */
431 status_t SMC_SetPowerModeVlls(SMC_Type *base);
432 #endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
433
434 /*!
435 * @brief Gets the reset source status which caused a previous reset.
436 *
437 * This function gets the current reset source status. Use source masks
438 * defined in the smc_reset_source_t to get the desired source status.
439 *
440 * Example:
441 @code
442 uint32_t resetStatus;
443
444 // To get all reset source statuses.
445 resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll;
446
447 // To test whether the MCU is reset using Watchdog.
448 resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog;
449
450 // To test multiple reset sources.
451 resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
452 @endcode
453 *
454 * @param base SMC peripheral base address.
455 * @return All reset source status bit map.
456 */
SMC_GetPreviousResetSources(SMC_Type * base)457 static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base)
458 {
459 return base->SRS;
460 }
461
462 /*!
463 * @brief Gets the sticky reset source status.
464 *
465 * This function gets the current reset source status that has not been cleared
466 * by software for some specific source.
467 *
468 * Example:
469 @code
470 uint32_t resetStatus;
471
472 // To get all reset source statuses.
473 resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll;
474
475 // To test whether the MCU is reset using Watchdog.
476 resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog;
477
478 // To test multiple reset sources.
479 resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
480 @endcode
481 *
482 * @param base SMC peripheral base address.
483 * @return All reset source status bit map.
484 */
SMC_GetStickyResetSources(SMC_Type * base)485 static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base)
486 {
487 return base->SSRS;
488 }
489
490 /*!
491 * @brief Clears the sticky reset source status.
492 *
493 * This function clears the sticky system reset flags indicated by source masks.
494 *
495 * Example:
496 @code
497 // Clears multiple reset sources.
498 SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin));
499 @endcode
500 *
501 * @param base SMC peripheral base address.
502 * @param sourceMasks reset source status bit map
503 */
SMC_ClearStickyResetSources(SMC_Type * base,uint32_t sourceMasks)504 static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks)
505 {
506 base->SSRS = sourceMasks;
507 }
508
509 /*!
510 * @brief Configures the reset pin filter.
511 *
512 * This function sets the reset pin filter including the enablement/disablement and filter width.
513 *
514 * @param base SMC peripheral base address.
515 * @param config Pointer to the configuration structure.
516 */
517 void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config);
518
519 /*!
520 * @brief Sets the system reset interrupt configuration.
521 *
522 * For a graceful shut down, the MSMC supports delaying the assertion of the system
523 * reset for a period of time when the reset interrupt is generated. This function
524 * can be used to enable the interrupt.
525 * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
526 * For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows:
527 * SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
528 *
529 * @param base SMC peripheral base address.
530 * @param intMask Bit mask of the system reset interrupts to enable. See
531 * smc_interrupt_enable_t for details.
532 */
SMC_SetSystemResetInterruptConfig(SMC_Type * base,uint32_t intMask)533 static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask)
534 {
535 base->SRIE = intMask;
536 }
537
538 /*!
539 * @brief Gets the source status of the system reset interrupt.
540 *
541 * This function gets the source status of the reset interrupt. Use source masks
542 * defined in the smc_interrupt_enable_t to get the desired source status.
543 *
544 * Example:
545 @code
546 uint32_t interruptStatus;
547
548 // To get all reset interrupt source statuses.
549 interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll;
550
551 // To test whether the reset interrupt of Watchdog is pending.
552 interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog;
553
554 // To test multiple reset interrupt sources.
555 interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin);
556 @endcode
557 *
558 * @param base SMC peripheral base address.
559 * @return All reset interrupt source status bit map.
560 */
SMC_GetResetInterruptSourcesStatus(SMC_Type * base)561 static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base)
562 {
563 return base->SRIF;
564 }
565
566 /*!
567 * @brief Clears the source status of the system reset interrupt.
568 *
569 * This function clears the source status of the reset interrupt. Use source masks
570 * defined in the smc_interrupt_enable_t to get the desired source status.
571 *
572 * Example:
573 @code
574 uint32_t interruptStatus;
575
576 // To clear all reset interrupt source statuses.
577 MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll);
578
579 // To clear the reset interrupt of Watchdog.
580 SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog);
581
582 // To clear multiple reset interrupt sources status.
583 SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin));
584 @endcode
585 *
586 * @param base SMC peripheral base address.
587 * @param All reset interrupt source status bit map to clear.
588 */
SMC_ClearResetInterruptSourcesStatus(SMC_Type * base,uint32_t intMask)589 static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask)
590 {
591 base->SRIF = intMask;
592 }
593
594 #if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE)
595 /*!
596 * @brief Sets the core software reset feature configuration.
597 *
598 * The MSMC supports delaying the assertion of the system reset for a period of time while a core
599 * software reset is generated. This allows software to recover without reseting the entire system.
600 * This function can be used to enable/disable the core software reset feature.
601 * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
602 * For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows:
603 * SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
604 *
605 * @param base SMC peripheral base address.
606 * @param intMask Bit mask of the core software reset to enable. See
607 * smc_interrupt_enable_t for details.
608 */
SMC_SetCoreSoftwareResetConfig(SMC_Type * base,uint32_t intMask)609 static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask)
610 {
611 base->CSRE = intMask;
612 }
613 #endif /* FSL_FEATURE_SMC_HAS_CSRE */
614
615 /*!
616 * @brief Gets the boot option configuration.
617 *
618 * This function gets the boot option configuration of MSMC.
619 *
620 * @param base SMC peripheral base address.
621 * @return The boot option configuration. 1 means boot option enabled. 0 means not.
622 */
SMC_GetBootOptionConfig(SMC_Type * base)623 static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base)
624 {
625 return base->MR;
626 }
627
628 #if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM)
629 /*!
630 * @brief Sets the force boot option configuration.
631 *
632 * This function sets the focus boot option configuration of MSMC. It can force the corresponding
633 * boot option config to assert on next system reset.
634 *
635 * @param base SMC peripheral base address.
636 * @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not.
637 */
SMC_SetForceBootOptionConfig(SMC_Type * base,uint32_t val)638 static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val)
639 {
640 base->FM = val;
641 }
642
643 #if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR)
644 /*!
645 * @brief Enables the conresponding SRAM array in low power retention mode.
646 *
647 * This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is
648 * disabled, and only in RUN mode.
649 *
650 * @param base SMC peripheral base address.
651 * @param arrayIdx Index of responding SRAM array.
652 * @param enable Enable the SRAM array in low power retention mode.
653 */
SMC_SRAMEnableLowPowerMode(SMC_Type * base,uint32_t arrayIdx,bool enable)654 static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
655 {
656 if (enable)
657 {
658 base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */
659 }
660 else
661 {
662 base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */
663 }
664 }
665 #endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */
666
667 #if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR)
668 /*!
669 * @brief Enables the conresponding SRAM array in STOP mode.
670 *
671 * This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes.
672 * When disabled, the corresponding SRAM array is powered off in STOP modes.
673 *
674 * @param base SMC peripheral base address.
675 * @param arrayIdx Index of responding SRAM array.
676 * @param enable Enable the SRAM array in STOP modes.
677 */
SMC_SRAMEnableDeepSleepMode(SMC_Type * base,uint32_t arrayIdx,bool enable)678 static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
679 {
680 if (enable)
681 {
682 base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */
683 }
684 else
685 {
686 base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */
687 }
688 }
689 #endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */
690
691 #endif /* FSL_FEATURE_SMC_HAS_FM */
692
693 /*@}*/
694
695 #if defined(__cplusplus)
696 }
697 #endif /* __cplusplus*/
698
699 /*! @}*/
700
701 #endif /* _FSL_MSMC_H_ */
702
