Home
last modified time | relevance | path

Searched refs:SIRCDIV (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c33 #define SCG_SIRCDIV_SIRCDIV1_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV…
34 #define SCG_SIRCDIV_SIRCDIV2_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV…
35 #define SCG_SIRCDIV_SIRCDIV3_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV3_MASK) >> SCG_SIRCDIV_SIRCDIV…
443 SCG->SIRCDIV = in CLOCK_InitSirc()
Dfsl_clock.h1260 uint32_t reg = SCG->SIRCDIV; in CLOCK_SetSircAsyncClkDiv()
1275 SCG->SIRCDIV = reg; in CLOCK_SetSircAsyncClkDiv()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16191 __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ member
DRV32M1_zero_riscy.h17019 __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ member