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Searched refs:SIRCCSR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c450 SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode; in CLOCK_InitSirc()
453 while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK)) in CLOCK_InitSirc()
462 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc()
476 SCG->SIRCCSR = 0U; in CLOCK_DeinitSirc()
485 if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */ in CLOCK_GetSircFreq()
Dfsl_clock.h1300 return (bool)(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK); in CLOCK_IsSircValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16190 …__IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x… member
DRV32M1_zero_riscy.h17018 …__IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x… member