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Searched refs:SIM_FCFG2_MAXADDR2_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17923 #define SIM_FCFG2_MAXADDR2_MASK (0x3F0000U) macro
17925 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR2_SHIFT)) & SIM_FCFG2_MAXADDR2_MASK)
DRV32M1_zero_riscy.h18751 #define SIM_FCFG2_MAXADDR2_MASK (0x3F0000U) macro
18753 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR2_SHIFT)) & SIM_FCFG2_MAXADDR2_MASK)