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Searched refs:SIM_FCFG1_FLSAUTODISWD_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17892 #define SIM_FCFG1_FLSAUTODISWD_MASK (0x3FF8U) macro
17894 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISWD_SHIFT)) & SIM_FCFG1_FLSAUTODISWD_MASK)
DRV32M1_zero_riscy.h18720 #define SIM_FCFG1_FLSAUTODISWD_MASK (0x3FF8U) macro
18722 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISWD_SHIFT)) & SIM_FCFG1_FLSAUTODISWD_MASK)