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Searched refs:SIM_FCFG1_FLSAUTODISEN_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17885 #define SIM_FCFG1_FLSAUTODISEN_MASK (0x4U) macro
17891 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISEN_SHIFT)) & SIM_FCFG1_FLSAUTODISEN_MASK)
DRV32M1_zero_riscy.h18713 #define SIM_FCFG1_FLSAUTODISEN_MASK (0x4U) macro
18719 … (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISEN_SHIFT)) & SIM_FCFG1_FLSAUTODISEN_MASK)