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Searched refs:SEMA42_RSTGT_R_RSTGMS_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17733 #define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) macro
17735 … (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
DRV32M1_zero_riscy.h18561 #define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) macro
18563 … (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)