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Searched refs:SCR (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_msmc.c15 #define CONFIG_NORMAL_SLEEP SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk
16 #define CONFIG_DEEP_SLEEP SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk
247 EVENT->SCR = (EVENT->SCR & ~0x03) | (1 << 1); in SMC_SetPowerModeVlls()
Dfsl_lpi2c.h939 base->SCR = LPI2C_SCR_RST_MASK; in LPI2C_SlaveReset()
940 base->SCR = 0; in LPI2C_SlaveReset()
951 base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); in LPI2C_SlaveEnable()
Dfsl_lpi2c.c1139 …base->SCR = LPI2C_SCR_FILTDZ(slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filter… in LPI2C_SlaveInit()
1579 if ((base->SCR & LPI2C_SCR_SEN_MASK) && s_lpi2cSlaveIsr) in LPI2C_CommonIRQHandler()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h10239 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
DRV32M1_zero_riscy.h10383 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member