Home
last modified time | relevance | path

Searched refs:SCG_VCCR_DIVSLOW_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16455 #define SCG_VCCR_DIVSLOW_MASK (0xFU) macro
16475 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK)
DRV32M1_zero_riscy.h17283 #define SCG_VCCR_DIVSLOW_MASK (0xFU) macro
17303 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK)