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Searched refs:SCG_VCCR_DIVCORE_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16518 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro
16538 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)
DRV32M1_zero_riscy.h17346 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro
17366 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)