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Searched refs:SCG_SOSCCSR_SOSCVLD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c349 while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) in CLOCK_InitSysOsc()
382 if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */ in CLOCK_GetSysOscFreq()
Dfsl_clock.h1211 return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK); in CLOCK_IsSysOscValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16717 #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) macro
16723 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
DRV32M1_zero_riscy.h17545 #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) macro
17551 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)