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Searched refs:SCG_SOSCCSR_SOSCEN_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c345 tmp8 |= SCG_SOSCCSR_SOSCEN_MASK; in CLOCK_InitSysOsc()
Dfsl_clock.h525 kSCG_SysOscEnable = SCG_SOSCCSR_SOSCEN_MASK, /*!< Enable OSC clock. */
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16675 #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) macro
16681 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
DRV32M1_zero_riscy.h17503 #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) macro
17509 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)