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Searched refs:SCG_SIRCDIV_SIRCDIV1 (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c444 …SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(con… in CLOCK_InitSirc()
Dfsl_clock.h1271 reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider); in CLOCK_SetSircAsyncClkDiv()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16843 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDI… macro
DRV32M1_zero_riscy.h17671 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDI… macro