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Searched refs:SCG_SIRCCSR_SIRCVLD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c453 while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK)) in CLOCK_InitSirc()
485 if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */ in CLOCK_GetSircFreq()
Dfsl_clock.h1300 return (bool)(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK); in CLOCK_IsSircValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16813 #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) macro
16819 … (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
DRV32M1_zero_riscy.h17641 #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) macro
17647 … (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)