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Searched refs:SCG_SIRCCSR_SIRCEN_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c450 SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode; in CLOCK_InitSirc()
Dfsl_clock.h557 kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK, /*!< Enable SIRC clock. */
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16785 #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) macro
16791 … (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK)
DRV32M1_zero_riscy.h17613 #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) macro
17619 … (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK)