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Searched refs:SCG_ROSCCSR_ROSCVLD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c655 if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */ in CLOCK_GetRtcOscFreq()
Dfsl_clock.h1461 return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK); in CLOCK_IsRtcOscValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17072 #define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) macro
17078 … (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)
DRV32M1_zero_riscy.h17900 #define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) macro
17906 … (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)