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Searched refs:SCG_LPFLLTCFG_TRIMDIV_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17243 #define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1F00U) macro
17245 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK)
DRV32M1_zero_riscy.h18071 #define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1F00U) macro
18073 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK)