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Searched refs:SCG_LPFLLDIV_LPFLLDIV3_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c42 #define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_L…
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17204 #define SCG_LPFLLDIV_LPFLLDIV3_MASK (0x70000U) macro
17216 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV3_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV3_MASK)
DRV32M1_zero_riscy.h18032 #define SCG_LPFLLDIV_LPFLLDIV3_MASK (0x70000U) macro
18044 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV3_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV3_MASK)