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Searched refs:SCG_LPFLLDIV_LPFLLDIV2_VAL (Results 1 – 1 of 1) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c41 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
777 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()