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Searched refs:SCG_LPFLLCSR_LPFLLVLD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c714 while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
756 if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1545 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17153 #define SCG_LPFLLCSR_LPFLLVLD_MASK (0x1000000U) macro
17159 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK)
DRV32M1_zero_riscy.h17981 #define SCG_LPFLLCSR_LPFLLVLD_MASK (0x1000000U) macro
17987 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK)