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Searched refs:SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c721 while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17125 #define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (0x400U) macro
17131 …(((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)
DRV32M1_zero_riscy.h17953 #define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (0x400U) macro
17959 …(((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)