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Searched refs:SCG_LPFLLCSR_LPFLLSEL_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c734 if (reg & SCG_LPFLLCSR_LPFLLSEL_MASK) in CLOCK_DeinitLpFll()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17160 #define SCG_LPFLLCSR_LPFLLSEL_MASK (0x2000000U) macro
17166 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK)
DRV32M1_zero_riscy.h17988 #define SCG_LPFLLCSR_LPFLLSEL_MASK (0x2000000U) macro
17994 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK)