Home
last modified time | relevance | path

Searched refs:SCG_LPFLLCSR_LPFLLCMRE_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17139 #define SCG_LPFLLCSR_LPFLLCMRE_MASK (0x20000U) macro
17145 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK)
DRV32M1_zero_riscy.h17967 #define SCG_LPFLLCSR_LPFLLCMRE_MASK (0x20000U) macro
17973 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK)