Home
last modified time | relevance | path

Searched refs:SCG_HCCR_DIVSLOW (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16576 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_S… macro
DRV32M1_zero_riscy.h17404 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_S… macro