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Searched refs:SCG_FIRCDIV_FIRCDIV1 (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c545 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
Dfsl_clock.h1359 reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider); in CLOCK_SetFircAsyncClkDiv()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16971 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDI… macro
DRV32M1_zero_riscy.h17799 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDI… macro