Home
last modified time | relevance | path

Searched refs:SCG_FIRCCSR_FIRCSTEN_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.h641 kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK, /*!< Enable FIRC in stop mode. */
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16892 #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) macro
16898 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
DRV32M1_zero_riscy.h17720 #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) macro
17726 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)